Current Issue : July - September Volume : 2014 Issue Number : 3 Articles : 5 Articles
The process of creating secure embedded systems with sensor network is highly challenging and complex, particularly from a\ntechnical viewpoint.Asecure embedded system is used for a specific purpose and operation, and needs hardware-software codesign\nmethodology. As such, there are many considerations in terms of system design when the system developer creates or constructs\na secure embedded system with sensor network. However, there is a lack of research into quality models in the area of secure\nembedded systems in sensor network. This paper seeks to redress this issue by presenting a quality model for a secure embedded\nsystem with sensor network. Each quality for the secure embedded system is constructed according toDeLone andMcLean�s success\ninformation system, and has subcriteria according to their characteristics. The present research also focuses on making a quality\nmodel network which considers the correlation between the qualities� attributes....
Brain Machine Interface (BMI) system is very useful modus operandi for the disabled or the crippled person to express his emotions and feelings to someone else with the help of EEG signals coming out of the brain. We know that, the human brain is made up of billions of interconnected neurons about the size of a pinhead. As neurons interact with each other, patterns manifest as singular thoughts such as a math calculation. As a by-product, every interaction between neurons creates a miniscule electrical discharge, measurable by EEG (electroencephalogram) machines. This system enables people with severe motor disabilities to send command to electronic devices with the help of their brain waves. These signals can be used to control any electronic devices like mouse cursor of the computer, a wheel chair, a robotic arm etc. The research in the area of BCI system (or BMI) uses the sequence of 256 channel EEG data for the analysis of the EEG signals coming out of the brain by using traditional gel based multi sensor system, which is very bulky and not convenient to use in real time application. So this particular work proposes a convenient system to analyze the EEG signals, which uses few dry sensors as compared to the traditional gel based multi sensor system with wireless transmission technique for capturing the brain wave patterns and utilizing them for this application. The goal of this research is to improve quality of life for those with severe disabilities....
The synchronous model of computation divides the program execution into a sequence of logical steps. On the one\nhand, this view simplifies many analyses and synthesis procedures, but on the other hand, it imposes restrictions on\nthe modeling and optimization of systems. In this article, we introduce refined clocks in imperative synchronous\nlanguages to overcome these restrictions while still preserving important properties of the basic model. We first\npresent the idea in detail and motivate various design decisions with respect to the language extension. Then, we\nsketch all the adaptations needed in the design flow to support refined clocks....
In the last few years speed of processor is increased every six month to one year. We have requirement of parallel processing for some scientific research work such as bio-medical research, earthquake analysis and for high definition video. For parallel processing we have to require multi-core architecture. Multi-core means more than one similar type of core always in even no. is integrated on single chip with given area. With multi-core architecture we can improve system performance up to some limitation because we can’t reduce transistor size. If we reduce transistor size then density of transistor on chip is increase but heating effect increase it affects working of processor and some time processor chip become useless. With help of reconfigurable heterogeneous architecture we can improve the performance of the system. In heterogeneous architecture all core are different in size, frequency and functionality also different instruction set is used for programming. Heterogeneous architecture means combination of CPU, GPU, DSP and FPGA processor integrate on single chip. In today’s PC and laptop there are CPU and GPU both are integrate on single chip, with this combination we can achieve high speed. In future different combination like CPU with DSP, CPU with FPGA and all are integrate on single chip for improvement of speed and performance of system with limited area and given power budget....
In the design of embedded systems, hardware and software need to be co-explored together to meet targets of\nperformance and energy. With the use of application-specific instruction-set processors, as a stand-alone solution or\nas a part of a system on chip, the customization of processors for a particular application is a known method to reduce\nenergy requirements and provide performance. In particular, processor designs with exposed data paths trade\ncompile time complexity for simplified control hardware and lower running costs. An exposed data path also allows\nthe removal of unused components of interconnection network, once the application is compiled.\nIn this paper, we propose the use of a compiler technique for processors with exposed data paths, called software\nbypassing. Software bypassing allows the compiler to schedule data transfers between execution units directly,\nbypassing the use of a general-purpose register file, increasing scheduling freedom, with reduced dependencies\ninduced by the reuse of registers, decreasing the number of read and write accesses to register files, and allowing the\nuse of register files with less read and write ports while maintaining or improving performance and maintaining\nreprogrammability. We compare our proposal against an architecture exploration technique, connectivity reduction,\nwhich finds in compiled application all interconnection network components that are used and removes those which\nare not, leading to an energy-efficient application-specific instruction-set processor.\nWe observe that the use of software bypassing leads to improvements in application speed, with architectures having\nthe smallest number of register file ports consistently outperforming architectures with larger number of ports, and\nreduction in energy consumption. In contrast, connectivity reduction maintains the same application speed, reduces\nenergy consumption, and allows for increase in processor frequency; however, with the clock frequency increased to\nmatch the performance of software bypassing, energy consumption grows. We also observe that in case\nreprogrammability is not an issue, the most energy-efficient solution is a combination of software bypassing and\nconnectivity reduction....
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